Serial Port Memory Technology (SPMT) uses high speed serial link technology even in memory area. This serial link provides several benefits including low power and reduced pin counts and connects between host and memory. Although one serial link can support several Gbps of bandwidth, if memory bandwidth requirement gets higher than that supported by a single serial line, multiples serial links must be used to support the additional bandwidth requirement.
For example, referring now to FIG. 1A illustrating conventional frame aligning, a command 108 is encoded in multiple bits 110 and is sent bit by bit via a high speed link 102 as indicated by a second signal serial data 102. When this serialized data 102 arrive at the receiver side, these data bits 110 are parallelized again and stored in a bit packet, such as a 20-bit packet 112 as indicated by a third signal deserialized data 104. However, this “deserialized” 20-bit data 104 cannot be used to decode because the command 108 can start in the middle of this received data. For example, the deserialized data 104 at the receiver side is received as “fghabcde” 116 even though the host sent “abcdefgh” 118. In other words, the starting position (or header) of the command 108 is needed to be identified, while the host data 100 is sent by the host in a predefined pattern. For example, in this case, the predefined pattern is set to “abcdefgh” 118. After finding the starting position, the correct command 114 is obtained by shifting two adjacent deserialized data 104. This technique is referred to as “frame aligning”, and the predefined pattern 118 used for this aligning is referred to as “SYNC” character.
If, however, a host has to send a large amount of data, the data is to be transferred via multiple serial links 152-162 as referenced in FIG. 1B that illustrates conventional frame and port aligning. Properties of multiple high speed links are different from each other. Usually a sampling front-end block (e.g., clock data recovery (CDR)) samples incoming serial data 102 and passes it to a deserializer block in a given clock. Also, flight times from the host to the receiver for each channel are not exactly the same. For example, the host sends a set of data at the same time, while one receiver samples data at a first clock and the other receiver samples it at a second clock. To compensate for this flight time difference or path difference, it is necessary to add one cycle delay 164 to the channels 158 where the data arrives earlier than the channels 162, respectively, where it arrives later. This process is referred to as “virtual lane alignment” 164 for computer expansion cards. Another alignment process 166 of seeking and aligning the header of each data segment is also performed along with the process of virtual lane alignment.
Now referring to FIG. 2, illustrating conventional process to measure and compensate path difference, to identify path differences, distinguishable predefined patterns are determined and communicated to various channels. For example, FIG. 2 illustrates a method to measure path differences and make the necessary data alignment with respect to various channels for computer expansion cards. For example, data is sent within a data stream at processing block 202, and the host inserts two COMMA patterns into the data stream at processing block 204 and sends the data at processing block 206. When a receiver probes this pattern at processing block 208, it checks the arrival time of the COMMA character on each channel or port at processing block 210. It further determines whether the same COMMA character appeared earlier at another channel at decision block 212. If yes, and there is a channel which does not yet have the COMMA character, the receiver inserts a one cycle delay for the data flowing through that channel at processing block 214. If not, the process continues with the delay.
FIG. 3 illustrates a conventional architecture 300 for providing virtual lane alignment (e.g. frame aligning and port aligning). When data is received via a serial link, it is sampled by a Clock Data Recovery (CDR) block that extracts clock (rck) from the incoming data to minimize the sampling error. Then, it passes the results of it to an aligner block with combining 4 bits. The first component of the aligner block is a deserializer 302 that combines five sequential incoming 4-bit data to 20-bit data using a depth of five shift registers 308. The second component is a frame aligner 304 to make the output start at a correct position. Since the deserializer 302 is running at a recovered clock (rck) and the frame aligner 304 is running at a system clock (clk), two registers of the five registers 308 are located to resolve the problem while crossing the clock domain. The combination may contain a register and a shifter. The third component is a port aligner 306. If a one cycle delay is required, the output from a register located in the port aligner 306 is selected instead of the data coming from the frame aligner 304.
The aligning of data (e.g., frame aligning, port aligning), or compensating skew between multiple channels, is commonly used in various serial link technologies, such as PCI-Express. However, SPMT has rather short interconnection between host and memory compared to other serial technologies, and it means that data skew on channels could be limited in relatively short amount. The difference comes out to be 0 or 1 in host clock cycle. It uses one kind of SYNC character to set up the outgoing and incoming channels and does not send distinguishable or special character to measure data skew. Thus, for example, the conventional bulky First In First Out (FIFO)-based technique cannot be applied to compensate data skew while a channel is in a setup period.